The present invention is related to data transmission, and, more particularly, to transmitting data at a rate slower than a system clock signal speed during link initialization in conformance with a SpaceWire application.
SpaceWire is the common name associated with the European Cooperation For Space Standardization Specification ECSS-E-50-12A. According to this specification the data rate on the wire must be slowed down to 10 Mhz during link initialization. Data Throttling is a way to meet this requirement without having to adjust the transmit clocks.
Prior auto-detect art has been developed that involves on-chip generation of a 10 Mhz clock, multiplexing with the full speed clock to create a qualified clock, and distribution of this clock on a dedicated clock network. This method proved to be unworkable when used in an FPGA implementation and when coupled with an additional requirement to drive this qualified clock off-chip. Data Throttling removes the need to create the derived clock and also the need to drive this clock off chip. The present invention therefore makes the implementation of a SpaceWire protocol handler on an FPGA more easily realizable. It can also be carried over to ASIC implementations.
An example of a prior art auto-detect circuit 100 is shown in FIG. 1. Circuit 100 includes a multiplexer 102, a D-type flip-flop 104, and a transmit buffer 106. The D-input of the D-type flip-flop receives input Transmit data. The two inputs of multiplexer 102 receives a normal Transmit clock and a slower 10 Mhz clock used during link initialization. The output of multiplexer 102 is coupled to the clock input of flip-flop 104. The output of the multiplexer provides one of the two possible clock signals in the “Txq_clk” signal depending upon the state of the multiplexer control signal (“Link_run”). Note that in FIG. 1, circuit 100 includes a multiplexer 102 in the clock path, complicating the clock tree and making FPGA implementation difficult.
What is desired is a circuit and method for providing two clock signals for Data Throttling in a SpaceWire application without the necessity of multiplexing the clock signal that is suitable for use in single or multiple bit applications.